FIG. 6 is a circuit diagram illustrating a conventional parallel-input and series-output type shift register circuit. This shift register circuit consists of selector circuits 41 and 42 and a D flip-flop circuit 43. The selector circuit 41 consists of two-input NOR gates 1, 3, and 5, and the selector circuit 42 consists of two-input NOR gates 2, 4, and 6. The D flip-flop circuit 43 consists of two-input NOR gates 7 to 14. Thus, the conventional shift register circuit consists of fourteen two-input NOR gates 1 to 14.
Reference characters A, B, /A, and /B designate input data, C and /C output data, S and /S selection signals, and CK and /CK clock signals. The phase differences between A and /A, B and /B, C and /C, S and /S, CK and /CK are respectively 180.degree..
Since each of the two-input NOR gates 1 to 14 is a DCFL (Direct Coupled FET Logic) circuit, each NOR gate consists of three MESFETs (Metal Semiconductor FET) as shown in FIG. 8.
A description is given of the operation.
When the logic value of the selection signal S is "1" and the logic value of the reverse selection signal /S is "0", "0" is attained at the output node N13 of the NOR gate 3 to which the selection signal S is applied, and reverse data /A is attained at the output node N11 of the NOR gate 1 to which the reverse selection signal /S is applied because the input data A applied to the NOR gate 1 is reversed. Then, data A is attained at the output node N21 of the NOR gate 5 because the reverse data /A input to the NOR gate 5 is reversed. The data A thus selected in the selector circuit 41 is input to the NOR gate 7 of the D flip-flop circuit 43. During the process in the selector circuit 41, the input data A passes through two NOR gates 1 and 5.
When the logic value of the clock signal CK which drives the D flip-flop circuit 43 is "0", reverse data /A is attained at the output node N31 because the data A input to the NOR gate 7 is reversed. The reverse data /A from the NOR gate 7 is reversed twice while passing through the NOR gates 9 and 10, and reverse data /A is attained at the output node N42 of the NOR gate 10. During the process, the data passes through three NOR gates 7, 9, and 10. At this time, since the logic value of the reverse clock signal /CK is "1", "0" is attained at the output nodes N51 and N52 of the NOR gates 11 and 12, so that outputs from the NOR gates 13 and 14 constituting the flip-flop, i.e., the output data C and /C from the shift register circuit, hold the present output values.
When the logic value of the reverse clock signal /CK is "0", the reverse data /A from the NOR gate 10 is reversed in the NOR gate 12 and data A is attained at the output node N52. Then, the data A is reversed twice while passing through the NOR gates 14 and 13, so that data A is output from the NOR gate 13 as the output data C from the shift register circuit. During the process, the data passes through three NOR gates 12, 14, and 13.
The process from inputting the reverse input data /A to outputting the reverse output data /C is identical to the process described above.
In the conventional shift register circuit, the input data A (/A) has to pass through eight NOR gates until it is output as the output data C (/C).
When the logic value of the selection signal S is "0" and the logic value of the reverse selection signal /S is "1", the input data B is output as the output data C and the reverse input data /B is output as the reverse output data /C. Also in this case, the input data B (/B) has to pass through eight NOR gates until it is output as the output data C (/C).
In the coventional shift register circuit, either of the input data A and B (/A and /B) is selected by the selection signal S (/S), and the selected data is synchronized with the clock signal CK (/CK) to attain the output data C (/C).
FIG. 5 is a circuit diagram illustrating a conventional four-bit shift register circuit which is achieved by connecting three shift register circuits shown in FIG. 6 in series. In FIG. 5, reference numeral 31 designates a D flip-flop circuit, and numerals 32, 33, and 34 designate shift register circuits. Reference characters D1, /D1, D2, /D2, D3, /D3, D4, and /D4 are input parallel data, and characters D0 and /D0 designate output serial data. The phase differences between D1 and /D1, D2 and /D2, D3 and /D3, D4 and /D4 are respectively 180.degree..
The operation of the shift register circuit will be described using FIGS. 5, 6, and 7.
For example, the input parallel data D3 is input to the shift register circuit 33 and synchronized with the clock signal CK, and then it is output to the shift register circuit 34. At this time, the data D3 taken in the flip-flop circuit 43 due to the fall of the clock CK is delayed by two NOR gates at the output node N21. Then, the data D3 at the output node N21 is synchronized and latched due to the fall of the clock signal /CK and appears at the output node N41. At this time, the data is delayed by three NOR gates. The data at the node N41 is synchronized and latched due to the fall of the reverse clock signal /CK and, thereafter, it is output as the output data D0 which is further delayed by three NOR gates. In this way, the data D3 input to the shift register circuit 34 has been delayed by eight NOR gates in total when it is output as the output serial data D0.
As described above, since the input parallel data is synchronized with the clock signal CK in each shift register circuit, the delay time (t.sub.1 +t.sub.2) of the data in the shift register circuit has to be within a time interval equivalent to one cycle (T) of the clock signal CK, i.e., t.sub.1 +t.sub.2 has to be shorter than T (refer to FIG. 7). In other words, the delay time of the data in the conventional shift register circuit is equivalent to the delay time of eight two-input NOR gates, so that the time interval equivalent to the cycle T must be longer than the delay time of eight two-input NOR gates in order to operate the shift register circuit normally. Therefore, it is difficult to increase the operation speed of the shift register circuit.